STM32F4的GPIO使用_stm32f4 0xc000000-CSDN博客 (2024)

一.GPIO时钟使能
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)；

• 参数RCC_AHB1Periph可选择的范围如下：

#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200)#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400)

• 参数NewState可选择的范围如下：

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;

• 使能与去使能

 if (NewState != DISABLE) { RCC->AHB1ENR |= RCC_AHB1Periph; } else { RCC->AHB1ENR &= ~RCC_AHB1Periph; }

通过改写外设时钟使能寄存器(RCC_AHB1ENR) 使能和去使能外设

• RCC的定义
  就是RCC_TypeDef结构体的地址
  RCC的边界地址为：0x4002 3800 - 0x4002 3BFF（大小0x3FF）
  所以RCC_BASE就是0x4002 3800

#define RCC ((RCC_TypeDef *) RCC_BASE)typedef struct{ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved, 0x1C */ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved, 0x3C */ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ uint32_t RESERVED4; /*!< Reserved, 0x5C */ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */} RCC_TypeDef;

（可以看出来结构体大小4乘32个byte，明显小于0x3FF）

二.GPIO初始化
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)

• 结构体GPIO_TypeDef

typedef struct{ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */} GPIO_TypeDef;

• GPIOx的选择范围

#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

边界地址图（似乎没有JK，但是和GPIOI和CRC间留了0x800的位置）

• 结构体GPIO_InitTypeDef
  用于设置IO口，以及端口模式寄存器 (GPIOx_MODER)、端口输出类型寄存器 (GPIOx_OTYPER)、端口输出速度寄存器 (GPIOx_OSPEEDR)、端口上拉/下拉寄存器 (GPIOx_PUPDR)

typedef struct{ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIOMode_TypeDef */ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIOSpeed_TypeDef */ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. This parameter can be a value of @ref GPIOOType_TypeDef */ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of @ref GPIOPuPd_TypeDef */}GPIO_InitTypeDef;

• IO口的选择范围

#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */

• GPIO_Mode的选择范围
  用于端口模式寄存器 (GPIOx_MODER)的配置
  分别是输入(IN)、输出(OUT)、复用(AF)和模拟(AN)
  其中复用就是，使用IO的特殊功能usart、spi等等
  模拟就是采集和输出模拟量用的ADC、DAC

typedef enum{ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */}GPIOMode_TypeDef;

32位的寄存器每个IO口的模式配置占用两位

• GPIO_Speed的选择范围
  用于端口输出类型寄存器 (GPIOx_OTYPER) 的配置
  分别是推挽(PP)、开漏(OD)
  推挽可以正常输出高低电平，开漏要输出高电平需要外部上拉电阻

typedef enum{ GPIO_OType_PP = 0x00, GPIO_OType_OD = 0x01}GPIOOType_TypeDef;

32位的寄存器前面16位给每个IO口配置输出类型，后面16位预留

• GPIO_Speed的选择范围
  用于端口输出速度寄存器 (GPIOx_OSPEEDR)的配置
  分别是2 MHz（低速）、：25 MHz（中速）、50 MHz（快速）
  以及100 MHz（高速）

typedef enum{ GPIO_Low_Speed = 0x00, /*!< Low speed */ GPIO_Medium_Speed = 0x01, /*!< Medium speed */ GPIO_Fast_Speed = 0x02, /*!< Fast speed */ GPIO_High_Speed = 0x03 /*!< High speed */}GPIOSpeed_TypeDef;

32位的寄存器每个IO口的速度配置占用两位

• GPIO_PuPd的选择范围
  用于端口上拉/下拉寄存器 (GPIOx_PUPDR)的配置
  分别是无上拉下拉、上拉、下拉，还有一个保留

typedef enum{ GPIO_PuPd_NOPULL = 0x00, GPIO_PuPd_UP = 0x01, GPIO_PuPd_DOWN = 0x02}GPIOPuPd_TypeDef;

32位的寄存器每个IO口的上下拉配置占用两位

输出和复用模式下的配置表：

输入和模拟模式下的配置表：